Rishi Bala
Electrical and Computer Engineering Honors · UT Austin
Rishi Bala
Hi. I'm Rishi Bala.
I'm a student at UT Austin pursuing degrees in Electrical and Computer Engineering and Business.
I'm passionate about hardware engineering and seeing hard problems through to a working result. This fall, I've been working as a Hardware Engineering Intern at Base Power in Austin, doing R&D and debugging grid inverters. Besides engineering, my hobbies include anything outdoors, whether that's intramural pickleball or a run, as well as playing and listening to music as an avid jazz drummer. I love trying new restaurants and rooting for the Philadelphia Eagles or Phillies every week.
At UT Austin, I'm the Controls System Lead for Longhorn Racing Electric, where I own the car’s electronics architecture, from KiCad schematic and PCB layout through FreeRTOS firmware and safety logic. Outside the car, I've worked on RTL projects in SystemVerilog, including a market making engine and a UVM-verified pattern-matching accelerator. I also recently finished an internship at IPC Systems in New York City working with low-level hardware and firmware in C/C++ and Rust.
Controls System Lead
Longhorn Racing – Electric · August 2025 – Present
C · STM32 · CAN · FreeRTOS · KiCad
- Implemented real-time torque arbitration, torque vectoring, and traction control across all drive modes with deterministic CAN I/O.
- Built STM32 embedded control and telemetry systems with CAN networking, multi-sensor interfacing, and real-time firmware.
- Integrated safety interlocks, fault detection, and watchdog logic across all vehicle subsystems for competition reliability.
- Designed an automotive-grade wiring harness, including connector selection, crimping, CAN routing, and full-vehicle integration.
- Coordinated cross-functional integration with mechanical and high-voltage subteams, logging 250+ miles of vehicle testing and achieving a top-5 finish at the Formula SAE International Competition.
Embedded Firmware Intern
IPC Systems · May 2026 – September 2026
C · C++ · Rust · GStreamer · Wayland
- Replaced polling-based turret screenshot delivery with live streaming by benchmarking VNC and WebRTC pipelines on embedded Linux BSP hardware, measuring end-to-end frame latency to drive a production protocol decision for financial trading floors.
- Instrumented the embedded turret diagnostics pipeline, pulling live performance metrics from all trading floor endpoints.
- Extended the Rust/Tauri hardware interface with WAMP command surfaces, bridging the turret BSP to a desktop viewer.
- Worked with senior engineers to design the hardware-software stack covering BSP daemons in C/C++ with GStreamer and Wayland, an encrypted transport layer, and the Rust/Tauri viewer, tracing the full signal path from turret BSP to trading floor desktop.
VEX Robotics
Captain, Head Builder, Design, CAD · September 2021 – May 2025
Fusion 360 · CAD · Team Leadership
- Captained a six-person VEX team; spent 20+ hours each week leading team meetings and mentoring younger students.
- Used Autodesk Fusion 360 for CAD; documented each robot iteration in an award-winning engineering notebook.
- 1x World Finalist, 1x Worlds Division Champion, 1x Worlds Division Finalist, 2x New Jersey Tournament Champion.
- Also served as a VEX IQ Instructor, teaching students basic robotics techniques and block coding throughout the year.
Physics and ME Research Internship
NJIT · Prof. Ravindra & Prof. Mani · June – August 2024
Fusion 360 · CAD · Research
- Co-authored two review papers on magnetotactic bacteria (MTB) and ferrofluids.
- Researched applications of MTB and magnetosomes; surveyed ferrofluid usage in cancer therapies.
- Used CAD to design and produce an array of milli-scale electromagnetic coils driven by H-bridges to control miniature robotic arms.
Portfolio
See my Github for the full code and in-depth writeups.
Vehicle Control Unit (VCU)
July 2026 – Present
- Designed and built the VCU end to end in KiCad around an STM32G474; architected the analog front end (TVS, dividers, RC filtering, op-amp buffers) sizing every channel for STM32 ADC integrity.
- Arbitrated torque across APPS, regen, and torque-vectoring inputs, resolving driver intent against grip and thermal limits; wrote the ready-to-drive state machine and sensor plausibility checks in FreeRTOS.
- Built hardware-only safety logic (BSPD, shutdown sequencing) enforced independently of firmware; sensed both ends of the 24V shutdown loop so firmware can localize whether it opened upstream or at the VCU’s own relay.
FPGA Pattern-Matching Accelerator with Cache Hierarchy
June 2026 – August 2026
- Built an FPGA Aho-Corasick multi-pattern matching accelerator in SystemVerilog on an Arty A7 for streaming byte inputs.
- Placed the oversized transition table behind a latency-modeled memory, fronted by an SRAM cache exploiting state locality; swept LRU, FIFO, and random replacement against a novel static placement pinning high-traffic automaton rows in BRAM.
- Static placement hit 34 vs. 26 for FIFO/random (31% improvement, zero warmup overhead), with no runtime cost where access is statically fixed.
- Verified all four replacement policies in UVM with 0 errors and 0 fatals across a 47-byte multi-pattern stream; wrote a Python reference model to generate Aho-Corasick automata and transition tables as ground truth.
FPGA-Based CME Market Making Engine
May 2026 – June 2026
- Designed a fully pipelined, CPU-free market making system in SystemVerilog on a Xilinx Artix-7, spanning a complete Ethernet/TCP/IP stack, CME MDP 3.0 market data ingestion, and iLink 3 FIXP order submission across 25 RTL modules.
- Implemented a CME MDP 3.0 pipeline decoding SBE-encoded UDP multicast packets, with a 10-level order book featuring gap detection and snapshot-based sequence recovery.
- Built a quoting engine computing VWAP mid-price via a pipelined 64-bit integer divider, adjusting quotes for inventory skew and an OFI signal from real-time aggressor trade data.
- Wrote self-checking testbenches for all 25 modules with reference-model checking; brought the full design up on an Arty A7 with a DP83848 MII PHY.
Thermal Sensor Module (TSM)
August 2025 – April 2026
- Led development of the TSM: a module combining radiator fan control with integrated cooling loop and flow rate monitoring for the LHRe race car.
- Owned the full design cycle: component selection, schematic design, PCB layout, soldering, testing, and firmware development.
- Wrote latency-optimized firmware using FreeRTOS on an STM32 microcontroller; developed a CAN-based telemetry system for live data across all vehicle subsystems.
Embedded Shuffleboard
March 2026 – April 2026
- Built a multiplayer embedded shuffleboard platform as the ECE319H (Embedded Systems) final project.
- Implemented mixed-signal I/O, comparator logic with multiplexer selection, visual/auditory feedback, and an 8-segment display driver.
- Wrote embedded firmware in C to handle collision physics, input devices, and SPI communication with the LCD and speaker/amplifier.
YerraGlasses
December 2025 – March 2026
- Designed audio-augmented smart glasses using an ESP32-S3 and dual I2S Class-D audio amplifiers for real-time auditory feedback.
- Developed embedded ML using neural processing unit object detection to convert visual input into real-time audio cues.
- Created a custom space-constrained PCB and power system with USB-C, rail regulation, and I2S audio for low-latency operation.